Formal verification is an algorithmic-based approach that proves functional properties about an electronic design. Formal verification may include equivalence checking and model checking. Equivalence checking verifies the functional equivalence of two designs that are at the same or different abstraction levels (e.g., RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate). Equivalence checking is used for design implementation verification. Model checking verifies that the implementation satisfies the properties of the design. Although formal verification exhaustively proves functional properties about the electronic design, it does not check input/output dependencies included in the electronic design.